The present invention relates to a hard mask pattern in a semiconductor device and a method of forming the same and, more particularly, to a hard mask pattern in a semiconductor device and a method of forming the same for defining a plurality of active regions arranged in a matrix.
On a semiconductor substrate, a plurality of semiconductor elements such as transistors are formed that are electrically connected by metal wire. The metal wire and a junction area (for example, a source or a drain of the transistor) of the semiconductor substrate are electrically connected to each other via a contact plug.
In a dynamic random access memory (DRAM) device, a transistor is formed on the semiconductor substrate, and a storage node contact plug is formed. Prior to forming the contact plug, an interlayer insulating layer is formed and a contact hole is then formed in the interlayer insulating layer. The DRAM device is classified into various devices according to an arrangement of the transistor and a capacitor. In the 4F2 DRAM device, active regions are arranged in a matrix in a cell area. In particular, the active region is formed with a quadrangle shape (more particularly, a square shape). As integration of the device increases, a size of the active region or a distance between the active regions in the 4F2 DRAM device is less than a limitation of resolution of exposure equipment. Thus, when a process of forming the photoresist pattern for defining the active region is performed, an exposure process for the photoresist layer is carried out twice. Due to the above restriction, manufacturing costs are increased and it is difficult to reduce a resolution index (k1) below 0.20.